svdoc documentation

svdoc is a pydoc-style documentation generator for SystemVerilog RTL, built on pyslang. See the project repository for usage, design background, and roadmap status.

This site documents svdoc’s own Python implementation (the IR schema, parser, and renderers) — not the SystemVerilog docs svdoc generates.

Contents:

• Example output
  • Markdown output (svdoc example.sv)
  • HTML output
• API Reference
  • Doc IR
  • Parser
  • Markdown renderer
  • HTML renderer
  • Fixer
  • Site builder
  • CLI